Saving power in desktop and portable computers has become a very important parameter for the computer industry. The operable lifetime of a computer and/or its component circuitry may be increased by designing the components such that they can be powered down when they are not in use. Powering down a microprocessor, for example, must be done with care such that the processor is not powered down while executing an instruction or performing other work.
Many microprocessors include a phase-locked loop (PLL) circuit that multiplies an external reference clock frequency by some factor to generate the processor's internal system clock or core clock. The core clock is utilized by the processor during execution of its various functions and instructions. The core clock may be used to generate an internal bus clock that clocks the interface circuitry that communicates with external buses. One prior art 1/N mode bus clock generation scheme supports 1/N ratio of bus clocks to core clocks, where N is limited to 2, 3, or 4. In the 1/N mode clock scheme, a PLL generates a core clock signal which is at a frequency that is N times than the external reference clock received by the processor. The internal bus clock signal is then generated from the core clock to have the same frequency as the external reference clock. 2/N mode bus clock generation schemes also exist where for every N core clocks 2 internal bus clocks are generated.
In 1/N or 2/N mode, circuitry clocked by the internal bus clock operates in the "bus clock domain", and circuitry clocked by the core clock operates in the "core clock domain". In 1/N or 2/N mode, for each core clock within a bus clock period, there are associated synchronization state machines that ensure that information is transferred correctly between the bus clock domain and the core clock domain.
The core clock may be used to generate an internal general system clock that is coupled to the core circuitry of the processor such as the ALU, Cache, and instruction decode units. The core circuitry typically draws the majority of the power of the processor. Therefore, stopping the general system clock when the core circuitry is not required saves a significant amount of power. U.S. Pat. No. 5,473,767 describes a method and apparatus for controlling the stopping of the general system clock while guaranteeing the state of the processor prior to stopping the general system clock.
U.S. Pat. No. 5,473,767 discloses that one external pin STPCLK# is used to receive a STPCLK# signal and power down the processor. An internal clock signal is always left running to support circuits that often require a constant clock signal (e.g., snooping logic). These circuits will continue to draw power even when the processor is powered down. Therefore, what is needed is a mechanism that shuts off most of the circuits in the processor such that the process can draw even less power.
In the method and apparatus disclosed in U.S. Pat. No. 5,473,767, the PLL is always running. The PLL runs even when the processor is powered down by asserting the STPCLK# signal on the STPCLK# pin. The PLL will draw power while it is running. Therefore, what is needed is a mechanism for powering down the processor even further by shutting off the external reference clock and the PLL.
If the PLL is shut off by disabling the external clock signal in U.S. Pat. No. 5,473,767, it is undetermined in which core clock cycle and bus clock cycle the PLL stopped. Therefore, when the external reference clock signal is restarted and the PLL reacquires phase lock, the core clock and bus clock signals will be powered up in an indeterministic manner. That is, when the external reference clock is shut off and then turned on again, the PLL will be turned on non-deterministically such that the previous core clock/bus clock relationship may be lost. The prior described synchronization state machines between the bus clock domain and the core clock domain will then be unsynchronized, and the processor will not function properly. Therefore, what is needed is a mechanism for powering down the PLL in a deterministic manner and powering up the PLL in a deterministic manner such that internal bus clock and core clock maintain a predetermined relationship.
Processors incorporating the STPCLK# pin of U.S. Pat. No. 5,473,767 have also been difficult to test deterministically. Typically, the power drawn by the processor when the PLL is disabled is determined by measuring the power over time and observing when the power has stabilized. There is not currently a predetermined number of external reference clock cycles that a user can program into a testing apparatus such that the testing apparatus knows when to measure the specified minimum power drawn by the processor. Therefore, what is needed is a mechanism for specifying when the processor has powered down to a given powered down state in a deterministic manner, that is, in a certain number of external reference clock cycles.
Additionally, after the PLL is powered up in the 2/N clock mode, the first bus clock will either be aligned or misaligned with the core clock. Testing equipment must be programmed exactly to expect that the bus clock will be aligned or misaligned. Previously this could not be guaranteed in the processor making testing difficult if not impossible.
Therefore, what is also needed is a mechanism to ensure that after the PLL is powered up, there will be a determined alignment relationship between the bus clock and the core clock such that testing equipment may be programmed to test the processor.